Nanotube array and method for producing a nanotube array

ABSTRACT

A nanotube array and a method for producing a nanotube array. The nanotube array has a substrate, a catalyst layer, which includes one or more subregions, on the surface of the substrate and at least one nanotube arranged on the surface of the catalyst layer, parallel to the surface of the substrate. The at least one nanotube being arranged parallel to the surface of the substrate results in a planar arrangement of at least one nanotube. Therefore, the nanotube array of the invention is suitable for coupling to conventional silicon microelectronics. Therefore, according to the invention it is possible for a nanotube array to be electronically coupled to macroscopic semiconductor electronics. Furthermore, the nanotube array according to the invention may have an electrically insulating layer between the substrate and the catalyst layer. This electrically insulating layer preferably has a topography which is such that the at least one nanotube rests on the electrically insulating layer at its end sections and is uncovered in its central section. As a result of the surface of the at least one nanotube being partly uncovered, the uncovered surface of the nanotube can be used as an active sensor surface. For example, the uncovered surface of the nanotube can come into operative contact with an atmosphere which surrounds the nanotube array. The electrical resistance of a nanotube changes significantly in the presence of certain gases. Thus because the nanotube is clear and uncovered, the nanotube array can be used in many sensor applications.

[0001] The invention relates to a nanotube array and to a method forproducing a nanotube array.

[0002] As ongoing miniaturization continues, conventional siliconmicroelectronics will reach its limit. In particular, in the next tenyears the development of ever smaller and more densely arrangedtransistors, which by now amount to several hundred millions oftransistors per chip, will in principle encounter physical problems andlimits. When feature sizes drop below 80 nm, the components will bedisruptively affected by quantum effects, and these effects will becomedominant at feature sizes of approximately 30 nm. The increasingintegration density of the components on a chip also leads to a dramaticincrease in the waste heat which is generated.

[0003] Carbon nanotubes are known to be a possible successor technologyto conventional semiconductor electronics. By way of example, [1] givesan overview of this technology.

[0004] A nanotube is a single-walled or multiwalled, tube-like carboncompound. In the case of multiwalled nanotubes, at least one innernanotube is coaxially surrounded by an outer nanotube. Single-wallednanotubes typically have diameters of approximately one nanometer, whilethe length of a nanotube may be several hundreds of nanometers. The endsof a nanotube are often closed off by means of in each case half a partof a fullerene molecule.

[0005] The extended π-electron system and the geometric structure ofnanotubes result in good electrical conductivity, and consequentlynanotubes are suitable for the construction of circuits with dimensionsin the nanometer range. It is known from [2] that the electricalconductivity of carbon nanotubes may significantly exceed that of metalsof the same dimensions.

[0006] The diameter and chirality of a nanotube are parameters on whichthe electrical conductivity of the nanotube is dependent. The electricalconductivity of a nanotube may furthermore be altered by applying anelectric field and/or doping the nanotubes with boron nitride. In thelatter case, it is customary to refer to a nanotube doped with boronatoms and nitrogen atoms or to a boron nitride nanotube.

[0007] On account of the conductivity of nanotubes and on account of thepossibility of adjusting this conductivity in the manner describedabove, nanotubes are suitable for a wide range of applications, forexample for the electrical connection technology in integrated circuits,for microelectronics components and for electron emitters.

[0008] Furthermore, it is known from [3] that the electrical resistanceof nanotubes changes by approximately three orders of magnitude within afew seconds if nanotubes are exposed to a gas, such as for example anitrogen dioxide (NO₂) gas or an ammonia (NH₃) gas. In an NH₃atmosphere, the electrical conductivity of the nanotubes is reduced,which can be explained by a shift in the valence band edge to well belowthe Fermi level of the nanotubes with a resultant charge carrierdepletion. Conversely, the electrical conductivity of the nanotubesrises by approximately three orders of magnitude if the nanotubes areexposed to an NO₂ atmosphere in a concentration of approximately 200ppm. This can be explained by the fact that the Fermi energy of thenanotubes is shifted closer to the valence band and accordingly thenumber of charge carriers in the nanotubes increases.

[0009] For nanotubes to be used in microelectronics, it is oftendesirable for nanotubes to be applied in a defined manner at specificlocations of a substrate. By way of example, nanotubes can be used asconductors in order to couple two conductor levels of a microcircuitelement which are electrically separated from one another. For thispurpose, it is necessary for nanotubes to be grown only where acorresponding electric coupling is desired, whereas the other regions ofthe substrate should remain clear of nanotubes in order to preventelectrical short circuits.

[0010] To achieve this objective, it is known to use a sputteringprocess to apply a metal which catalyzes the growth of nanotubes, forexample iron, to a substrate which has been patterned, for example, withphotoresist. Then, the patterned photoresist and the metal locatedthereon are removed using a lift-off method. As a result, the metalmaterial remains only on locations on the substrate which werepreviously uncovered. The catalytically active metal which remains isused as a matrix for nanotubes to grow on.

[0011] Vapor deposition processes (chemical vapor deposition, CVD) areknown processes for the production of carbon nanotubes. In the CVDprocess, the components and dopants are brought together as gases, ifappropriate with additional carrier gases, in a reaction space, wherethe deposition on the substrate takes place. To produce carbon nanotubesusing the CVD process, the carbon source used is often methane (CH₄) oralternatively acetylene (C₂H₂).

[0012] Methods for producing nanotubes and nanowires on catalyticallyactive surfaces using the CVD process have been described, for example,in [4] and [5]. The method described in those documents makes itpossible to produce carbon nanotubes which are arranged vertically on asubstrate.

[0013] However, in the method which is described in [4], the base has toconsist of aluminum. This is a disadvantageous restriction in terms ofthe material. Furthermore, the method described in [4] results inrelatively large, multiwalled carbon nanotubes with diameters ofapproximately 50 nm. Also, the carbon nanotubes produced using themethod described are oriented perpendicular to the substrate and cantherefore only be integrated in conventional silicon microelectronics toa limited extent.

[0014] The method for producing carbon nanotubes which is described in[5] results in the formation of an arrangement of carbon nanotubes indensely packed blocks. These blocks are defined by the catalyst (forexample iron) which has been vaporized on by means of a mask. However,it is difficult to produce a regular arrangement using the productionmethod described. Since once again it is only possible to producenanotubes which are oriented perpendicular to the surface of thesubstrate, there are considerable limitations to the way in which thenanotubes can be coupled to conventional silicon microelectronics.

[0015] To summarize, methods for producing an array of carbon nanotubeswhich are known from the prior art have a number of drawbacks. Forexample, the nanotubes produced using the methods described are orientedperpendicular to the surface of the substrate. Furthermore, according tothe known methods it is difficult to produce structurally defined arraysof nanotubes. There is no precisely defined direction of growth for thenanotubes on the surface of a catalyst material. The lack of order whichresults and the fact that the nanotubes are oriented perpendicular tothe substrate surface means that the nanotube arrays which are knownfrom the prior art cannot be coupled to conventional siliconmicroelectronics or can only do so with difficulty.

[0016] It is known from [6] to form catalyst islands on a substrate. Acarbon nanotube which is coupled to two catalyst islands can be formedusing a CVD process if a carbon nanotube which grows from a catalystisland happens randomly to grow toward a second catalyst island.Therefore, once again according to [6] it is not possible to produce aspatially sufficiently well defined array of nanotubes.

[0017] The invention is based on the problem of providing a spatiallywell defined array of planar-oriented nanotubes.

[0018] The problem is solved by a nanotube array and a method forproducing a nanotube array having the features of the independent patentclaims.

[0019] A nanotube array has a substrate, a catalyst layer, whichincludes one or more subregions, on the surface of the substrate and atleast one nanotube arranged on the surface of the catalyst layer,parallel to the surface of the substrate.

[0020] The at least one nanotube being arranged parallel to the surfaceof the substrate results in a planar arrangement of at least onenanotube. Therefore, the nanotube array of the invention is suitable forcoupling to conventional silicon microelectronics. Therefore, accordingto the invention it is possible for a nanotube array to beelectronically coupled to macroscopic semiconductor electronics.

[0021] Furthermore, the nanotube array according to the invention mayhave an electrically insulating layer between the substrate and thecatalyst layer. This electrically insulating layer preferably has atopography which is such that the at least one nanotube rests on theelectrically insulating layer at its end sections and is uncovered inits central section.

[0022] As a result of the surface of the at least one nanotube beingpartly uncovered, the uncovered surface of the nanotube can be used asan active sensor surface. By way of example, the uncovered surface ofthe nanotube can come into operative contact with an atmosphere whichsurrounds the nanotube array. As has been stated above, the electricalresistance of a nanotube changes significantly in the presence ofcertain gases (for example NO₂ or NH₃), with the result that, on accountof the nanotube being clear and uncovered, the nanotube array can beused in many sensor applications.

[0023] Furthermore, in the nanotube array, the subregions of thecatalyst layer may be electrically decoupled from one another.Irrespective of this, it is also possible for the nanotubes of the arrayto be electrically decoupled from one another.

[0024] If the nanotube array has a plurality of subregions of thecatalyst layer which are electrically decoupled from one another and/ora plurality of nanotubes which are electrically decoupled from oneanother, it is possible for a plurality of nanotubes to be used inparallel and independently of one another as components of an electriccircuit (for example as electrical conductors) and/or as sensors.

[0025] According to the nanotube array of the invention, the nanotubeswhich are decoupled from one another are provided in planar form, i.e.they are arranged parallel to the surface plane of the substrate. Theyare preferably arranged parallel to and in each case at a distance fromone another. This arrangement increases the mechanical stability of thenanotubes, since the latter are arranged in the horizontal direction,with the result that bending of the sensitive nanotubes is obviouslyavoided. By contrast, according to the prior art nanotubes projectvertically out of a substrate surface and are therefore susceptible tomechanical disruption. The nanotube array of the invention issufficiently mechanically robust to allow it to be used under laboratoryconditions.

[0026] Furthermore, the nanotube array may have a circuit device bymeans of which the nanotubes can be driven and/or read individually. Byway of example, the electrical resistance of each of the nanotubes canbe recorded individually by means of the circuit device. The circuitdevice may be a conventional microelectronic circuit. In this way, ananotube array is coupled to a conventional microelectronic circuit. Theplanar, horizontal arrangement of the nanotube is particularly suitablefor integration in silicon microelectronics. In particular, themicroelectronics may be provided as an integrated circuit in thesubstrate on which the at least one nanotube is also arranged.

[0027] Furthermore, at least one of the subregions of the catalyst layermay be at least partially surrounded by a further electricallyinsulating layer. In particular, the electrically insulating layer andthe further electrically insulating layer between which the catalystlayer is arranged may project laterally beyond the catalyst layer, inorder in this way to form a pore which can predetermine the direction ofgrowth of the nanotube parallel to the surface of the substrate. Thehorizontal pore evidently serves as a template for the growth of thenanotube. The pore is formed by two walls which project beyond thecatalyst layer on both sides and are formed by the electricallyinsulating layer and by the further electrically insulating layer. Thefirst electrically insulating layer and the second electricallyinsulating layer cover a large part of the surface of the catalystlayer, and only a small surface region of the catalyst layer remainsuncovered. This uncovered surface region is oriented perpendicular tothe substrate surface. If a nanotube is allowed to grow on this surfaceof the catalyst layer, the direction of growth is predetermined by thegeometry of the arrangement. The direction of growth of the carbonnanotube is perpendicular to the uncovered surface of the catalystlayer. Therefore, the direction of growth of the nanotube is horizontal,i.e. the nanotube grows in a direction which is parallel to the surfaceof the substrate. The first and second electrically insulating layersprojecting beyond the catalyst layer on both sides mechanically guidethe growth of the nanotube, with the result that the growth takes placein the horizontal direction parallel to the surface of the substrate.Since the direction of growth can be predetermined by the geometry ofthe pores, it is possible to achieve a defined structure of carbonnanotubes. This high degree of structural definition is advantageouswhen the nanotube array is being coupled to conventional siliconmicroelectronics.

[0028] A further advantage is that the nanotube array according to theinvention provides individual nanotubes rather than tufts of nanotubeswith diameters in the region of 50 nm, as in the prior art. The periodicprovision of pores also makes it possible to achieve a periodic array ofnanotubes. In this respect, it should be emphasized that the size of thepores can be selected to be sufficiently small for only a singlenanotube to grow in or from a pore.

[0029] The electrically insulating layer and/or the further electricallyinsulating layer are preferably made independently from one another fromone or a combination of the materials silicon nitride and silicondioxide. Since these materials do not have a catalytic action for thegrowth of nanotubes, the choice of these materials ensures that eachnanotube grows within a spatially accurately defined region in theinterior of the pore, i.e. on the surface of the catalyst layer.

[0030] In the nanotube array of the invention, it is also possible forat least one of the subregions of the catalyst layer to be at leastpartially surrounded by a layer for preventing diffusion. Obviously,this layer for preventing diffusion which at least partially surroundsat least one of the subregions of the catalyst layer prevents catalystmaterial from diffusing into adjacent layers or material of the adjacentlayers from diffusing into the catalyst layer. In particular, it isknown that catalytically active metals tend to diffuse into siliconlayers of, for example, a connected circuit. The layer for preventingdiffusion increases the service life of the nanotube array and ensuresthat it remains able to function. The layer for preventing diffusion ispreferably made from tantalum nitride material.

[0031] The catalyst layer is preferably made from one or a combinationof the materials nickel, iron and cobalt. Alternatively, it is possibleto use any other suitable material, in particular any other metal whichcatalyzes the growth of nanotubes.

[0032] It is preferable for the subregions of the catalyst layer to bearranged parallel to one another on the surface of the substrate. Thisparallel arrangement makes it possible to form pores which are arrangedin parallel.

[0033] The nanotube array may be used as a gas sensor. For this intendedapplication, it is necessary to have a nanotube with a substantiallyuncovered surface. Two electrodes are electrically coupled by means ofthe at last one nanotube. For the purposes of mechanical stabilization,the end sections of the at least one carbon nanotube may be arranged ona mechanically robust surface, for example an electrically insulatinglayer. The nanotube array described may be applied to a substrate, forexample a silicon wafer. The resistance of the at least one nanotubebetween the two electrodes can be recorded by a means for recording theelectrical resistance.

[0034] The use of the nanotube array as a gas sensor makes use of theabove-described physical effect whereby the electrical resistance ofnanotubes changes by approximately three orders of magnitude within afew seconds if a nanotube is exposed to a gas atmosphere, such as forexample nitrogen oxide (NO₂) or ammonia (NH₃). It should be emphasizedthat the nanotube array of the invention which is used as a gas sensoris not restricted to the detection of the two gases mentioned, butrather can also be used to detect other gases, such as oxygen (O₂),whose presence leads to a change in the electrical resistance of thenanotubes. The nanotube array of the invention provides a sufficientlyrobust gas sensor which is also sufficiently selectively sensitive withrespect to specific gases.

[0035] It should also be added that the two electrically conductiveelectrodes and the nanotubes may, for example, be integrated on asemiconductor chip, e.g. a CMOS chip. The means for recording theelectrical resistance may, for example, be an ohmmeter.

[0036] The nanotubes in the nanotube array may be carbon nanotubes.

[0037] The steps of the method for producing a nanotube array arereferred to by capital letters below for the sake of clarity.

[0038] In a step B of the method, a catalyst layer is applied to thesurface of the layer arrangement, the catalyst layer having one or moresubregions.

[0039] In a step F, at least one nanotube is grown on an uncovered partof the surface of a subregion of the catalyst layer, in such a mannerthat the at least one nanotube is arranged parallel to the surface ofthe layer arrangement.

[0040] Furthermore, in the method for producing a nanotube array, in afurther step A, the layer arrangement mentioned in step B can be formedby applying an electrically insulating layer to a substrate.

[0041] Also, in a step C, a further electrically insulating layer can beapplied to at least part of the surface of the layer arrangement, insuch a manner that the further electrically insulating layer at leastpartially covers at least one of the subregions of the catalyst layer.

[0042] Furthermore, in a step D, a trench can be etched into a surfaceregion of the layer arrangement.

[0043] In a step E, the catalyst layer can be partially etched back, insuch a manner that the electrically insulating layer and the furtherelectrically insulating layer project laterally beyond the catalystlayer, with the result that a pore as a guide for the growth of thenanotube is produced, predetermining the direction of growth of thenanotubes parallel to the surface of the substrate.

[0044] In a step F, at least one nanotube is grown on an uncovered partof the surface of a subregion of the catalyst layer, in such a mannerthat the at least one nanotube is arranged parallel to the surface ofthe layer arrangement.

[0045] According to a preferred configuration of the method according tothe invention for producing a nanotube array, the abovementioned steps Ato F are carried out in the following order:

[0046] First of all, in step A a layer arrangement is formed by applyingan electrically insulating layer to a substrate. Then, in a subsequentstep B, a catalyst layer is applied to the surface of the layerarrangement, the catalyst layer having one or more subregions. Then, ina further step C, a further electrically insulating layer is applied toat least part of the surface of the layer arrangement, in such a mannerthat the further electrically insulating layer partially covers at leastone of the subregions of the catalyst layer. Then, in a step D, a trenchis etched into a surface region of the layer arrangement. In asubsequent step E, the catalyst layer is partially etched back, in sucha manner that the electrically insulating layer and the furtherelectrically insulting layer project laterally beyond the catalystlayer, so that a pore which predetermines the direction of growth of thenanotube parallel to the surface of the substrate is produced. Then, ina step F, at least one nanotube is grown on an uncovered part of thesurface of a subregion of the catalyst layer, in such a manner that theat least one nanotube is arranged parallel to the surface of the layerarrangement.

[0047] Evidently, in step A, an electrically insulating layer is formedon a substrate. This can be effected in particular by silicon nitridematerial being deposited on a silicon wafer. In step B, a catalyst layeris applied to the surface of the layer arrangement, the catalyst layerhaving one or more subregions. This can be implemented by a nickel layerwhich is suitable for use as a catalyst layer being deposited on thesurface of the silicon nitride layer in a thickness of approximately 20nm and this nickel layer being patterned to form wires which preferablyrun substantially parallel to one another and are approximately 20 nmwide using the electron beam lithography process. In the following stepC, a further electrically insulating layer is applied to at least partof the surface of the layer arrangement, in such a manner that thefurther electrically insulating layer at least partially covers at leastone of the subregions of the catalyst layer. For this purpose, by way ofexample, silicon dioxide material can be deposited on the surface of thelayer arrangement and patterned by means of a photolithography method,so that the further electrically insulating layer remains only on partof the surface of the layer arrangement. In particular, the furtherelectrically insulating layer at least partially covers the catalystlayer. In the further step D, a trench is etched into a surface regionof the layer arrangement. This can be achieved by the uncovered regionof the electrically insulating layer being partially etched back bymeans of a photolithography process. In a further step E, the catalystlayer is partially etched back, in such a manner that the electricallyinsulating layer and the further electrically insulating layer projectbeyond the catalyst layer on both sides, so that a pore whichpredetermines the direction of growth of the nanotube parallel to thesurface of the substrate is produced. This method step can beimplemented by etching back the nickel layer by wet-chemical means andin this way producing pores. These pores are evidently formed as aresult of the nickel layer being etched back in a direction parallel tothe substrate surface to such an extent that both the silicon nitridelayer arranged beneath the nickel layer and the silicon dioxide layerarranged above the nickel layer project laterally beyond the nickellayer both above and below the latter. Then, in a step F, at least onenanotube is grown on an uncovered part of the surface of a subregion ofthe catalyst layer, in such a manner that the at least one nanotube isarranged parallel to the surface of the layer arrangement. The growth ofthe nanotubes can be effected, for example, using the vapor phaseepitaxy process.

[0048] The method for producing a nanotube array has a number ofadvantages. Geometrically ordered structures of nanotubes in a planararrangement can be produced by a combination of semiconductor technologynanostructuring techniques and a technique for growing nanotubes. Asdescribed above, the individual steps of the method are based on proven,standardized semiconductor technology processes. Therefore, there is noneed to develop new installations for carrying out the method accordingto the invention for producing the nanotube array. This saves time andcosts.

[0049] A major advantage of the method according to the inventionconsists in the fact that the pore geometry described above means thatthe production of nanotubes can be precisely predetermined with regardto dimensions and direction of growth. The cross-sectional area of ananotube is fixed by the dimension of the uncovered catalyst surface,since the nanotube growth can only start from a catalytically activematerial. According to the invention, the preferred direction of growthof a nanotube is predetermined simply by the normal vector of theuncovered catalyst surface and is additionally stabilized by theelectrically insulating layers arranged on both sides of the catalystlayer. This provides the nanotube with mechanical guidance during itsgrowth, with the result that the nanotube grows in a predeterminabledirection parallel to the surface of the substrate.

[0050] Furthermore, according to the invention the thickness of thecatalyst layer can be set accurately. According to the example describedabove, the thickness of the catalyst layer is, for example,approximately 20 nm. As a result of a sufficiently low thickness beingselected, it is ensured that only a single nanotube can grow on thepore.

[0051] According to another configuration of the method of the inventionfor producing a nanotube array, the sequence of the steps describedindividually above is altered compared to the exemplary embodimentdescribed above. According to the exemplary embodiment described here,the step referred to above as D is carried out after step A and beforestep B. Specifically, the steps are carried out in the following order:

[0052] First of all, in step A, a layer arrangement is formed byapplying an electrically insulating layer to a substrate. This step canbe implemented by depositing a silicon nitride layer on a silicon wafer.In a subsequent step D, a trench is etched into a surface region of thelayer arrangement. This can be achieved by photopatterning of theapplied silicon nitride layer followed by etching. Then, in a step B, acatalyst layer is applied to the surface of the layer arrangement, thecatalyst layer having one or more subregions. This can be implemented bya catalyst layer, for example a 20 nm thick nickel layer, beingdeposited on the surface of the layer arrangement and being patterned bymeans of electron beam lithography to form wires which run substantiallyparallel to one another and are approximately 20 nm thick. In asubsequent step C, a further electrically insulating layer is applied toat least part of the surface of the layer arrangement, in such a mannerthat the further electrically insulating layer at least partially coversat least one of the subregions of the catalyst layer. This method stepcan be implemented by firstly covering the surface of the layerstructure with photoresist and then patterning the latter by means of alithography process. Then, by way of example, a silicon nitride layer isdeposited on the layer arrangement by sputtering or evaporation coating.Then, the silicon nitride layer and the photoresist layer below it canbe removed from a subregion of the surface of the layer arrangementusing a lift-off method. As a result, a silicon nitride layer remainsonly on a desired surface region of the layer arrangement, according tothe invention only on the surface of the catalyst layer. Next, in asubsequent step E, the catalyst layer is partially etched back, in sucha manner that the electrically insulating layer and the furtherelectrically insulating layer project laterally beyond the catalystlayer, so that a pore which predetermines the direction of growth of thenanotube parallel to the surface of the substrate is produced. As hasalready been described above, this can be achieved by wet-chemicallyetching back nickel, so that pores remain. Then, in a further methodstep F, at least one nanotube is grown on the uncovered part of thesurface of a subregion of the catalyst layer, in such a manner that theat least one nanotube is arranged parallel to the surface of the layerarrangement. Nanotubes can be produced, for example, by vapor phaseepitaxy.

[0053] Furthermore, the method according to the invention may at asuitable point include a further method step in which at least in partat least one layer for preventing diffusion is introduced between atleast one subregion of the catalyst layer and the layers which adjointhe at least one subregion of the catalyst layer. When coupling thenanotube array to conventional silicon microelectronics, it isadvantageous to surround the catalytically active metal with diffusionbarriers, since the catalyst metal can thermally diffuse into siliconregions of a connected circuit. Tantalum nitride can be used as materialfor the layer for preventing diffusion.

[0054] The electrically insulating layer and/or the further electricallyinsulating layer may be made from one or a combination of the materialssilicon nitride and silicon dioxide. However, it is also possible to useany other material suitable for this purpose.

[0055] The catalyst layer is preferably produced from one or acombination of the materials nickel, iron and cobalt. Alternatively, itis possible to use any other material which catalyzes the growth ofnanotubes.

[0056] It should be noted that the at least one nanotube which isapplied to the arrangement according to the method is preferably acarbon nanotube.

[0057] Exemplary embodiments of the invention are illustrated in thefigures and are explained in more detail below:

[0058] In the drawing:

[0059]FIG. 1A shows a plan view of a nanotube array in accordance with afirst exemplary embodiment of the invention,

[0060]FIG. 1B shows a cross section through a nanotube array on sectionline I-I′ from

[0061]FIG. 1A, in accordance with the first exemplary embodiment of theinvention,

[0062]FIG. 1C shows a plan view of a nanotube array in accordance with asecond exemplary embodiment of the invention,

[0063]FIG. 1D shows a cross section through a nanotube array on sectionline II-II′ from

[0064]FIG. 1C in accordance with the second exemplary embodiment of theinvention,

[0065]FIG. 1E shows a plan view of a nanotube array in accordance with athird exemplary embodiment of the invention,

[0066]FIG. 1F shows a cross section through a nanotube array on sectionline III-III′ from

[0067]FIG. 1E in accordance with the third exemplary embodiment of theinvention,

[0068]FIG. 2 shows a cross section through a nanotube array inaccordance with an exemplary embodiment of the nanotube array accordingto the invention for use as a gas sensor,

[0069]FIG. 3A shows a plan view (left) and a cross section on sectionline IVa-IVa′ (right) of a layer arrangement following a first methodsection in accordance with a preferred exemplary embodiment of themethod according to the invention for producing a nanotube array,

[0070]FIG. 3B shows a plan view and a cross section on section lineIVb-IVb′ of a layer arrangement following a second method section inaccordance with a preferred exemplary embodiment of the method accordingto the invention for producing a nanotube array,

[0071]FIG. 3C shows a plan view and a cross section on section lineIVc-IVc′ of a layer arrangement following a third method section inaccordance with a preferred exemplary embodiment of the method accordingto the invention for producing a nanotube array,

[0072]FIG. 3D shows a plan view and a cross section on section lineIVd-IVd′ of a layer arrangement following a fourth method section inaccordance with a preferred exemplary embodiment of the method accordingto the invention for producing a nanotube array,

[0073]FIG. 3E shows a plan view and a cross section on section lineIVe-IVe′ of a layer arrangement following a fifth method section inaccordance with a preferred exemplary embodiment of the method accordingto the invention for producing a nanotube array,

[0074]FIG. 3F shows a plan view and a cross section on section lineIVf-IVf′ of a layer arrangement following a sixth method section inaccordance with a preferred exemplary embodiment of the method accordingto the invention for producing a nanotube array,

[0075]FIG. 3G shows a plan view and a cross section on section lineIVg-IVg′ of a layer arrangement following a seventh method section inaccordance with a preferred exemplary embodiment of the method accordingto the invention for producing a nanotube array,

[0076]FIG. 4A shows a plan view (left) and a cross section on sectionline Va-Va′ (right) of a layer arrangement following a first methodsection in accordance with a further preferred exemplary embodiment ofthe method according to the invention for producing a nanotube array,

[0077]FIG. 4B shows a plan view and a cross section on section lineVb-Vb′ of a layer arrangement following a second method section inaccordance with the further preferred exemplary embodiment of the methodaccording to the invention for producing a nanotube array,

[0078]FIG. 4C shows a plan view and a cross section on section lineVc-Vc′ of a layer arrangement following a third method section inaccordance with the further preferred exemplary embodiment of the methodaccording to the invention for producing a nanotube array,

[0079]FIG. 4D shows a plan view and a cross section on section lineVd-Vd′ of a layer arrangement following a fourth method section inaccordance with the further preferred exemplary embodiment of the methodaccording to the invention for producing a nanotube array,

[0080]FIG. 4E shows a plan view and a cross section on section lineVe-Ve′ of a layer arrangement following a fifth method section inaccordance with the further preferred exemplary embodiment of the methodaccording to the invention for producing a nanotube array,

[0081]FIG. 5A shows a cross section through a layer arrangementfollowing a first method section in accordance with a third preferredexemplary embodiment of the method according to the invention forproducing a nanotube array,

[0082]FIG. 5B shows a cross section through a layer arrangementfollowing a second method section in accordance with the third preferredexemplary embodiment of the method according to the invention forproducing a nanotube array,

[0083]FIG. 5C shows a cross section through a layer arrangementfollowing a third method section in accordance with the third preferredexemplary embodiment of the method according to the invention forproducing a nanotube array,

[0084]FIG. 5D shows a cross section through a layer arrangementfollowing a fourth method section in accordance with the third preferredexemplary embodiment of the method according to the invention forproducing a nanotube array.

[0085]FIG. 1A shows a first exemplary embodiment of a nanotube array 100of the invention, which includes: a substrate 101, a catalyst layer 102,which has one or more subregions, on the surface of the substrate 101and at least one nanotube 103 arranged on the surface of the catalystlayer 102, parallel to the surface of the substrate 101. In accordancewith the exemplary embodiment shown in FIG. 1A, the nanotube array 100has three subregions of the catalyst layer 102, in each case onenanotube 103 being arranged at each of the subregions of the catalystlayer 102. FIG. 1B shows a cross-sectional view on section line I-I′ ofthe nanotube array 100 shown in FIG. 1A.

[0086]FIG. 1C shows a nanotube array 110 in accordance with a secondexemplary embodiment of the invention. FIG. 1D shows a cross-sectionalview on section line II-II′ of the nanotube array 110 shown in FIG. 1C.Compared to the nanotube array 100, the nanotube array 110 additionallyincludes an electrically insulating layer 104 which is arranged betweenthe substrate 101 and the catalyst layer 102. The electricallyinsulating layer 104 has a topography, i.e. a surface structure, whichis such that the at least one nanotube 103 at its end sections 103 arests on the electrically insulating layer 104 and is clear in itscenter section 103 b.

[0087] As can be seen in particular from the plan view of the nanotubearray 110 shown in FIG. 1C, the subregions of the catalyst layer 102 areelectrically decoupled from one another. The subregions of the nanotubes103 are also electrically decoupled from one another.

[0088]FIG. 1E shows a plan view of a nanotube tube array 120 as a thirdexemplary embodiment of the invention. FIG. 1F shows a cross-sectionalview on section line II-III′ of the nanotube array 120 shown in FIG. 1E.The nanotube array 120, in addition to the features shown in thenanotube arrays 100, 110, also includes additional features: thenanotube array 120 shown in FIG. 1E, FIG. 1F has a circuit device 105,by means of which the nanotubes 103 can be driven and/or readindividually. Furthermore, in accordance with the nanotube array 120shown in FIG. 1E, FIG. 1F, all three subregions of the catalyst layer102 are surrounded by a further electrically insulating layer 106. Thefact that the electrically insulating layer 104 and the furtherelectrically insulating layer 106, between which the catalyst layer 102is arranged, project laterally beyond the catalyst layer 102 on bothsides results in the formation of a pore which can be used topredetermine the direction of growth of the nanotubes 103 parallel tothe surface of the substrate 101. Furthermore, as shown in FIG. 1F, atleast one of the subregions of the catalyst layer 102 is surrounded by alayer for preventing diffusion 107.

[0089] The nanotube array 120 can be coupled to external electronics,for example a CMOS circuit, by means of the circuit device 105. Asindicated in FIG. 1E, each of the three nanotubes 103 is coupled to aconnection electrode 108 of the circuit device 105 via the electricallyconductive catalyst layer 102.

[0090] If three horizontal pores, each of which serves as a template forthe growth of one of the three nanotubes 103, have been produced by thegeometric arrangement of the electrically insulating layer 104, of thethree subregions of the catalyst layer 102 and of the furtherelectrically insulating layer 106 which can be seen from FIG. 1F, theresult is a planar arrangement of nanotubes 103. By preciselypredetermining the location of growth and direction of growth, it ispossible to produce arrays of nanotubes which can be structuredgeometrically accurately.

[0091] The electrically insulating layer 104 and/or the furtherelectrically insulating layer 106 are made from one or a combination ofthe materials silicon nitride and silicon dioxide. According toalternative exemplary embodiments of the invention, the electricallyinsulating layer 104 and/or the further electrically insulating layer106 may be made from another suitable material which must have theproperty of having no catalytic action with regard to the growth ofnanotubes 103. The nanotube array 120 includes a layer for preventingdiffusion 107, which is preferably made from tantalum nitride. Thisprevents material of the catalyst layer from diffusing into anyadjoining silicon regions of a coupled microelectronic circuit, forexample under thermal influences. Therefore, the layer for preventingdiffusion 107 acts as a diffusion barrier for the catalytically activematerial.

[0092] According to this exemplary embodiment, the catalyst layer 102 ismade from one or a combination of the materials nickel, iron and cobalt.However, it is also possible to use any other suitable material whichcatalyzes the growth of nanotubes 103. If, as symbolically indicated inFIG. 1E and FIG. 1F, the nanotubes 103 are to be coupled to connectionelectrodes 108 of an external circuit device 105 by means of thecatalyst layer 102, an electrically conductive material is to beselected for the catalyst layer 102.

[0093] The nanotubes 103 in the nanotube arrays 100, 110, 120 are carbonnanotubes.

[0094]FIG. 2 shows a gas sensor 200 as an example of an application forthe nanotube array according to the invention. The gas sensor 200 has apatterned substrate 201, an electrically insulating layer 202, anelectrically conductive catalyst layer 203, a further electricallyinsulating layer 204, a carbon nanotube 205 and an electrode 206.

[0095] The functionality of the gas sensor 200 is based on the physicaleffect described above whereby the electrical resistance of a carbonnanotube 205 is extremely sensitively dependent on the gas atmospheresurrounding the carbon nanotube 205. As described above, in an ammoniaatmosphere (NH₃), the electrical conductivity of carbon nanotubes isreduced by approximately three powers of ten. Conversely, the electricalconductivity increases by approximately three orders of magnitude if thecarbon nanotube 205 is exposed to a nitrogen dioxide (NO₂) atmosphere ina concentration of 200 ppm (parts per million, 10⁻⁶).

[0096] If the electrical resistance of the carbon nanotube 205 betweenthe electrically conductive layers 203 and 206 is taken in a means forrecording the electrical resistance (not shown in FIG. 2) when thesurface of the carbon nanotube 205 which is clear in its central section205 a is exposed to a specific gas atmosphere, the value of theelectrical resistance of the carbon nanotube 205 is a characteristicmeasure of the type or concentration of the gas which surrounds thecarbon nanotube 205. The means for recording the electrical resistanceis preferably integrated in the substrate. The carbon nanotube 205arranged between the electrically conductive catalyst layer 203 and theelectrically conductive electrode 206 is preferably to be provided witha surface which is substantially uncovered in its central section 205 a.By contrast, the end sections 205 b of the nanotube 205 are notuncovered, but rather are coupled to the further electrically insulatinglayer 204 or to the electrically conductive electrode 206.

[0097] To increase the measurement accuracy of the gas sensor 200, it ispossible for a plurality of carbon nanotubes 205, all or some of whichare exposed to a specific gas atmosphere, to be connected either inparallel or in series or partly in parallel and partly in series.Referring to FIG. 2, this can be achieved, for example, by theindividual carbon nanotubes 205 being arranged substantially parallel toone another in a plane perpendicular to the plane of the drawing.

[0098] The gas sensor 200 shown in FIG. 2 may, for example, be operatedas described below. The arrangement 200 is brought into operativecontact with a gas atmosphere which is to be detected. The means forrecording the electrical resistance can be used to determine theelectrical resistance of the carbon nanotube 205 between theelectrically conductive contacts 203, 206 of the carbon nanotube 205,the value of the electrical resistance of the carbon nanotube 205 beingcharacteristic of the concentration or nature of the surrounding gas. Asa result of the sensitive carbon nanotube 205 being applied to therobust electrically insulating layer 202 or to the robust patternedsubstrate 201, the gas sensor 200 is made sufficiently robust to besuitable for practical use in a laboratory.

[0099] The following text, referring to FIG. 3A, FIG. 3B, FIG. 3C, FIG.3D, FIG. 3E, FIG. 3F and FIG. 3G describes a first preferred exemplaryembodiment of the method according to the invention for producing ananotube array which includes the method steps A, B, C, D, E, F. Inaccordance with the exemplary embodiment described, these steps are tobe carried out in the order A, B, C, D, E, F. The left-hand side of FIG.3A, FIG. 3B, FIG. 3C, FIG. 3D, FIG. 3E, FIG. 3F and FIG. 3G in each caseshows a plan view of the layer arrangement which is in each caseobtained after the individual method steps have been carried out, whilethe right-hand side in each case shows an associated cross-sectionalview on section lines IVa-IVa′, IVb-IVb′, IVc-IVc′, IVd-IVd′, IVe-IVe′,IVf-IVf′ and IVg-IVg′ of this layer arrangement.

[0100] In step A, a layer arrangement 300 is formed by applying anelectrically insulating layer 301 to a substrate 302.

[0101] The layer structure 300 obtained after step A has been carriedout is shown in FIG. 3A. The substrate 302 is preferably a siliconwafer; alternatively, the substrate 302 may also be a glass substrate.By way of example, the electrically insulating layer 301 deposited onthe substrate 302 may be a silicon nitride layer or may alternatively bea silicon dioxide layer.

[0102] In step B, a catalyst layer 303 is applied to the surface of thelayer arrangement 300, the catalyst layer 303 having one or moresubregions.

[0103] After step B has been carried out, a layer arrangement 304 isobtained (cf. FIG. 3B). In accordance with the layer arrangement 304shown in FIG. 3B, the catalyst layer 303 has five subregions. Step B isimplemented by, in a first substep, depositing a catalyst layer 303 onthe surface of the layer arrangement 300. A 20 nm thick nickel layer isdeposited on the surface of the layer structure 300. This nickel layerwhich has been deposited over the entire surface of the layer structure300 is then patterned in a second substep using a suitable lithographyprocess, for example by means of electron beam lithography. It ispreferable for the nickel layer which has been deposited to be patternedin such a manner that wires with a diameter of 20 nm remain.

[0104] Then, in a step C, a further electrically insulating layer 305 isapplied to at least part of the surface of the layer arrangement 304, insuch a manner that the further electrically insulating layer 305 atleast partially covers at least one of the subregions of the catalystlayer 303.

[0105] The substeps of step C can be understood with reference to FIG.3C and FIG. 3D. In a first substep, the further electrically insulatinglayer 305 is applied to the surface of the layer arrangement 304. Thiscan be achieved, for example, by a silicon dioxide layer being appliedto the surface of the layer arrangement 304. This results in a layerarrangement 306 as shown in FIG. 3C. Then, in a second substep, thefurther electrically insulating layer 305 which has been applied ispatterned using a suitable lithography or etching process. This resultsin the layer arrangement 307 shown in FIG. 3D, in which a subregion ofthe further electrically insulating layer 305 partially covers thecatalyst layer 303.

[0106] In a subsequent step D, a trench 308 is etched into a surfaceregion of the layer arrangement 307.

[0107] This results in the layer arrangement 309 illustrated in FIG. 3E.Method step D is implemented by means of a suitable photolithographyprocess.

[0108] In a next method step E, the catalyst layer 303 is partiallyetched back, in such a manner that the electrically insulating layer 301and the further electrically insulating layer 305 project laterallybeyond the catalyst layer 303, so that a pore 310 which predeterminesthe direction of growth of the nanotube parallel to the surface of thesubstrate 302 is produced.

[0109] After this method step, the layer arrangement 311 illustrated inFIG. 3F is obtained. The formation of a pore 310 as a result of theelectrically insulating layer 301 and the further electricallyinsulating layer 305 projecting laterally beyond the catalyst layer 303on both sides substantially defines the way in which the subsequentgrowth of the nanotube takes place (cf. step F, below). Since nanotubespreferentially grow on catalytically active material, i.e. on uncoveredsurface regions of the catalyst layer 303, the “seed point” for thenanotube growth is defined. Furthermore, the direction of growth isdefined as a result of the electrically insulating layer 301 and thefurther electrically insulating layer 305 projecting beyond the catalystlayer 303. A guide or template for the growth of the nanotube isobviously provided. As a result, it is possible to use the pore geometryto control the diameter, direction of growth and arrangement of thenanotubes. In process engineering terms, the catalyst layer 303 can beetched back by means of wet-chemical etchback methods. For example, theprior art has disclosed methods which allow catalyst layers 303consisting, for example, of nickel to be etched back by wet-chemicalmeans.

[0110] In a subsequent step F, at least one nanotube 312 is grown on anuncovered part of the surface of a subregion of the catalyst layer 303,in such a manner that the at least one nanotube 312 is arranged parallelto the surface of the layer arrangement 311.

[0111] After step F has been carried out, the layer arrangement 313which is illustrated in FIG. 3G is obtained. The nanotubes 312 areproduced, for example, by means of vapor phase epitaxy. As stated above,the direction of growth and diameter of the nanotubes 312 can bepredetermined by the pores 310 and by the thickness of the catalystlayer 303.

[0112] The text which follows explains a second exemplary embodiment ofthe method according to the invention for producing a nanotube arraywith reference to FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D, FIG. 4E. Thisexemplary embodiment differs from the exemplary embodiment explainedabove substantially with regard to the order in which steps A to F arecarried out. The left-hand side of FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4Dand FIG. 4E in each case shows a plan view of the layer arrangementobtained after each of the individual method steps have been carriedout, while the right-hand side in each case shows an associatedcross-sectional view on section lines Va-Va′, Vb-Vb′, Vc-Vc′, Vd-Vd′ andVe-Ve′ of this layer arrangement.

[0113] The second exemplary embodiment of the method according to theinvention for producing a nanotube array includes the following steps:

[0114] In step A, a layer arrangement 400 is formed as a result of anelectrically insulating layer 401 being applied to a substrate 402.

[0115] The layer structure 400 shown in FIG. 4A is obtained after stepA. The electrically insulating layer 401 is a silicon nitride layer oralternatively a silicon dioxide layer, and the substrate 402 is asilicon wafer or alternatively a glass substrate.

[0116] In a step D which follows step A, a trench 403 is etched into asurface region of the layer arrangement 400.

[0117] The introduction of the trench 403 into the electricallyinsulating layer 401 on the surface of the substrate 402 is achieved byphotopatterning and subsequent etching of the surface of the layerstructure 400. After step D, which follows step A, has been carried out,the layer arrangement 404 shown in FIG. 4B is obtained.

[0118] In a step B which follows step D described above, a catalystlayer 405 is applied to the surface of the layer arrangement 404, thecatalyst layer 405 having one or more subregions.

[0119] In accordance with the layer arrangement 406 illustrated in FIG.4C, which is obtained after step B has been carried out, the catalystlayer 405 has five subregions. In practical implementation, the methodstep referred to as step B usually comprises a plurality of substeps. Ina first substep, a catalyst layer 405 is applied to the entire surfaceof the layer structure 404. By way of example, a layer of nickel whichis approximately 20 nm thick is deposited over the surface of the layerstructure 404. In a second substep of step B, the catalyst layer 405 ispatterned by means of a suitable lithography process, for example bymeans of electron beam lithography, in such a manner that one or moresubregions remain on the surface of the layer arrangement 404. Referringto FIG. 4C, after this substep five subregions of the catalyst layer 405remain on the surface of the layer structure. It is preferable for thecatalyst layer 405 to be patterned to form wires of a width ofapproximately nm. As shown in the cross-sectional view presented in FIG.4C, after the photopatterning material of the catalyst layer 405 remainson the surface of the layer structure 406 only in a region arranged tothe left of the trench 403.

[0120] In a subsequent step C, a further electrically insulating layer407 is applied to at least part of the surface of the layer arrangement406, in such a manner that the further electrically insulating layer 407at least partially covers at least one of the subregions of the catalystlayer 405.

[0121] The method step referred to as step C also includes a pluralityof substeps. In a first substep, a photoresist layer is deposited on thesurface of the layer structure 406. In a second substep, a lithographyprocess with a suitable mask is used to pattern the surface of the layerarrangement 406 covered by the photoresist. In a further substep, afurther electrically insulating layer 407, for example comprisingsilicon nitride material or silicon dioxide material, is deposited onthe surface of the layer arrangement 406, which has been provided withphotoresist and photopatterned, by means of a suitable semiconductortechnology process, for example by sputtering or evaporation coating. Ina further substep, the double layer composed of the photoresist layerand the electrically insulating layer 407 is removed from a subregion ofthe surface of the layer arrangement using a lift-off method. Whatremains is a layer arrangement which differs from the layer arrangement406 illustrated in FIG. 4C substantially through the fact that thefurther electrically insulating layer 407 remains in place in a surfaceregion of the layer arrangement which in accordance with thecross-sectional view of the layer arrangement is located to the left ofthe left-hand boundary of the trench 403.

[0122] In a subsequent method step E, the catalyst layer 405 ispartially etched back, in such a manner that the electrically insulatinglayer 401 and the further electrically insulating layer 407 projectlaterally beyond the catalyst layer 405, so that a pore 408 whichpredetermines the direction of growth of the nanotube parallel to thesurface of the substrate 402 is produced.

[0123] After method step E has been carried out, the layer arrangement409 shown in FIG. 4D is obtained. Step E can be implemented by etchingback the catalyst layer 405 by wet-chemical means and in this wayforming pores 408. By way of example, a catalyst layer 405 made fromnickel is etched back by means of a wet-chemical etching process. Asdescribed above, the formation of pores 408 for defining the directionof growth of a nanotube, the diameter of a nanotube and the productionof an ordered structure of nanotubes is essential.

[0124] In a subsequent method step F, at least one nanotube 410 is grownon an uncovered part of the surface of a subregion of the catalyst layer405, in such a manner that the at least one nanotube 410 is arrangedparallel to the surface of the layer arrangement 409.

[0125] After the method step F has been carried out, the layerarrangement 411 shown in FIG. 4E is obtained. Nanotubes 410 can beproduced, for example, by means of the vapor phase epitaxy process,which is known from the prior art.

[0126] Furthermore, the described method for producing a nanotube arraymay include the further step of introducing a layer for preventingdiffusion (not shown in the figures) between at least one subregion ofthe catalyst layer 405 and the adjoining layers 401, 407. This makes itpossible to prevent the material of the catalyst layer 405 fromdiffusing into regions of any connected external circuit (not shown inthe figures), for example as a result of thermal influences. The layerfor preventing diffusion (provided with reference numeral 107 in FIG.1F) is preferably made from tantalum nitride.

[0127] The electrically insulating layer 401 and/or the furtherelectrically insulating layer 407 are produced independently from oneanother from one or a combination of the materials silicon nitride andsilicon dioxide.

[0128] The catalyst layer 405 is preferably made from one or acombination of the materials nickel, iron and cobalt. Alternatively, anyother catalytically active material can be used to produce the catalystlayer 405.

[0129] According to the present exemplary embodiment, the nanotubes 410which are to be grown onto the layer arrangement 409 are carbonnanotubes.

[0130] The text which follows describes a further exemplary embodimentof the method according to the invention for producing a nanotube arraywhich is tailored to the use of the nanotube array which has beenproduced using the method as a gas sensor.

[0131] The method described below for the production of the gas sensoris described with reference to FIG. 5A, FIG. 5B, FIG. 5C, FIG. 5D.

[0132] In a first step A, a layer arrangement 504 is formed by applyingan electrically insulating layer 501, 502 to a substrate 503.

[0133] After step A has been carried out, the layer arrangement 504illustrated in FIG. 5B is obtained. Step A includes a plurality ofsubsteps. In a first substep, an electrically insulating layer isapplied to both main sides of a substrate 503. In FIG. 5A, these twolayers are referred to as first electrically insulating layer 501 andsecond electrically insulating layer 502. The substrate 503 ispreferably a silicon wafer, and the first electrically insulating layer501 and/or the second electrically insulating layer 502 are preferablymade from silicon nitride material or alternatively from silicon dioxidematerial. It is also possible for the first insulating layer 501 and thesecond electrically insulating layer 502 to be made from differentmaterials. To pattern the substrate 502, in a next substep first of allthe electrically insulating layer 501 which has been applied to a mainside of the substrate 503 is patterned by means of a suitablesemiconductor technology process in such a manner that a surface regionof the substrate 503 is uncovered in a central region of the layerarrangement 500. Evidently, a hole, for example a substantially circularor rectangular hole, is etched into the first electrically insulatinglayer 501. In a following substep, a suitable etching process is appliedto the layer structure in order to remove the material of the substrate503 from the central region of the arrangement, in which part of thesurface of the substrate has previously been uncovered by the etchingprocess. To do this, an etching process in which the etching chemicalsused are to be selected in such a way that they etch the material of thesubstrate 503 whereas the materials of the first electrically insulatinglayer 501 and of the second electrically insulating layer 502 are notattacked by the etching chemical is to be used. After the substepsdescribed have been carried out, the layer arrangement 500 shown in FIG.5A is obtained. In a following substep, the first electricallyinsulating layer 501 is removed from the surface of the layer structure500, resulting in the layer structure 504 shown in FIG. 5B. This can beachieved, for example, by means of a suitable etching process.

[0134] The method steps described below are carried out predominantly onthat main side of the second electrically insulating layer 502 which isremote from the substrate 503. To make this clearer in the drawings, inFIG. 5B the layer arrangement 504 has been rotated through an angle of180° with respect to the layer arrangement 500 shown in FIG. SA.

[0135] In a step B, a catalyst layer 505 is applied to the surface ofthe layer arrangement 504, the catalyst layer 505 having one or moresubregions.

[0136] The layer structure obtained after step B has been carried out isnot shown in the figures. Method step B is implemented by first of allapplying a catalyst layer 505 which completely covers the surface of thelayer structure 504 and then patterning this catalyst layer 505 by meansof a suitable semiconductor technology process, for example by means ofthe electron beam lithography process. By way of example, an iron layer,a cobalt layer or a nickel layer or a layer of any other material whichcatalyzes the growth of nanotubes can be applied and can be patterned toform wires with a thickness of, for example, 20 nm using the electronbeam lithography process. The individual subregions of the catalystlayer 505 cannot be seen from the cross-sectional views of the FIG. SC,FIG. SD.

[0137] In a subsequent method step C, a further electrically insulatinglayer 506 is applied to at least part of the surface of the layerarrangement, in such a manner that the further electrically insulatinglayer 506 at least partially covers at least one of the subregions ofthe catalyst layer 505.

[0138] Method step C is implemented by first of all applying a furtherelectrically insulating layer 506 which covers the entire surface of thelayer arrangement and patterning this layer by means of a suitablesemiconductor technology process. By way of example, the furtherelectrically insulating layer 506 is a silicon dioxide layer, or,alternatively, the further electrically insulating layer 506 may be asilicon nitride layer which is then patterned, for example, by means ofa photolithography method.

[0139] In the next method step D, a trench 507 is etched into a surfaceregion of the layer arrangement.

[0140] In practice, this step is implemented by patterning the surfaceof the layer arrangement, for example using a photolithography process.

[0141] In a method step E, the catalyst layer 505 is partially etchedback, in such a manner that the electrically insulating layer 502 andthe further electrically insulating layer 506 project laterally beyondthe catalyst layer 505, so that a pore 508 which predetermines thedirection of growth of the nanotubes parallel to the surface of thesubstrate 503 is produced.

[0142] This results in the layer structure 509 shown in FIG. 5C. Themethod step E can be implemented by etching back the catalyst layer 505by wet-chemical means in order in this way to produce a pore 508.

[0143] To enable the nanotube array which has been produced using themethod to be used as a gas sensor (for which use the maximum possiblepart of the surface of the nanotube should be uncovered), the exemplaryembodiment of the production method according to the invention describedincludes a few particular features. Since the nanotube which is to beapplied in a further method step must come into operative contact with asurrounding gas atmosphere, so that as a result of the operative contactthe electrical resistance of the nanotube changes in a manner which ischaracteristic of the surrounding gas, in the gas sensor produced the atleast one nanotube must be uncovered, i.e. exposed to the surroundinggas, in the largest possible surface region. To achieve this, in anintermediate method step E1, the second electrically insulating layer502 is partially etched back in a central region on its main side of thesecond electrically insulating layer which faces the substrate 503. Thisresults in the formation of the groove 510 which is illustrated in FIG.5D and is introduced into the second electrically insulating layer 502to a sufficient depth to produce a through-hole through the secondelectrically insulating layer 502 together with the trench 507.

[0144] Then, in a subsequent method step F, at least one nanotube 511 isgrown on an uncovered part of the surface of a subregion of the catalystlayer 505, in such a manner that the at least one nanotube 511 isarranged parallel to the surface of the layer arrangement.

[0145] The nanotubes 511 are produced, for example, by using the vaporphase epitaxy process. A pore 508 is formed on account of the secondelectrically insulating layer 502 (from below in accordance with FIG.5D) and the further electrically insulating layer 506 (from above inaccordance with FIG. 5D) projecting laterally beyond the catalyst layer505 on both sides. The nanotubes 511 can only start to grow from thesurface of a catalytically active layer. Therefore, the at least onenanotube 511 can only grow out of the pore 508, starting from theuncovered surface of the catalyst layer 505. Since the direction ofgrowth can be predetermined by the channel-like template which is formedby the second electrically insulating layer 502 and the furtherelectrically insulating layer 506, it is possible to define thedirection of growth of the nanotube 511 . Therefore, the invention makesit possible to ensure that the nanotube 511 shown in FIG. 5D can onlygrow in the horizontal direction, i.e. in a direction parallel to thesurface of the substrate 503. The diameter of the nanotube 511 can bepredetermined by the thickness of the catalyst layer 505. As a result,individual nanotubes 511 can be grown by suitably selecting thethickness of the catalyst layer 505.

[0146] For the nanotube array of the invention to be used as a gassensor, it is necessary to carry out a further additional step, sincethe use of the nanotube array as a gas sensor requires a physicalvariable of the nanotube which is sensitive to a surrounding gasatmosphere to be recorded. As described above, in particular theelectrical resistance of a nanotube is a variable which is sensitive tothe nature and concentration of a surrounding gas. Therefore, theelectrical resistance of the nanotube 511 has to be recorded, and forthis purpose the nanotube array which is to be used as a gas sensor isto be coupled to a means for recording the electrical resistance (notshown in the figures). For this purpose, electrical contact has to bemade with the at least one nanotube 511 on both sides, so that it can becoupled to the means for recording the electrical resistance via thesetwo electric contacts. Therefore, in a further additional step, it isnecessary to make electric contact with the uncovered end section 511 aof the nanotube 511 which is not coupled to the catalyst layer 505. Forthis purpose, an electrically conductive electrical contact 512 isapplied to the layer structure in order to be coupled to the uncoveredend section 511 a of the nanotube 511. The resulting layer structure 513is shown in FIG. 5D. FIG. 5D does not show the electrical contact madewith the other end section 511 b of the nanotube 51 , which is coupledto the catalyst layer 505. Electric contact has to be made with thisother end section 511 b of the nanotube 511 which is coupled to thecatalyst layer 505 too in order for it to be possible to record theelectrical resistance of the nanotube 511 between the two end sections511 a, 511 b of the nanotube 511.

[0147] After these method steps have been carried out, the layerstructure 513 shown in FIG. 5D, which can be used as a gas sensor, isobtained. It should be emphasized that the use of the nanotube array ofthe invention as a gas sensor is not restricted to the exemplaryembodiment shown in FIG. 5D. For example, it is possible for a pluralityof nanotubes 511 to be electrically connected in series, in order toincrease the overall resistance to be recorded and in this way toincrease the sensitivity of the gas sensor arrangement. Alternatively,it is also possible for a plurality of nanotubes 511 to be connected inparallel, in order for their electrical resistance to be recordedseparately for each nanotube and in this way to increase the detectionaccuracy by means of multiple measurement. It is also possible for someof the nanotubes 511 to be connected in parallel and for others of thenanotubes 511 to be connected in series. Furthermore, the way in whichthe nanotube array functions as a gas sensor is not restricted to theelectrical resistance of the nanotube 511 being recorded. It is alsopossible for any other physical parameter of the nanotube 511 which issensitive to a physical variable which is to be recorded to be measuredby means other than electrical.

1. A nanotube array, comprising: a substrate; a catalyst layer, whichincludes one or more subregions, on the surface of the substrate; atleast one nanotube arranged on the surface of the catalyst layer,parallel to the surface of the substrate; and a pore, the pore beingused to predetermine the direction of growth of the nanotube startingfrom the catalyst layer and parallel to the surface of the substrate. 2.The nanotube array as claimed in claim 1, further comprising anelectrically insulating layer between the substrate and the catalystlayer.
 3. The nanotube array as claimed in claim 2, further comprisingthe electrically insulating layer having a topography which is such thatthe at least one nanotube rests on the electrically insulating layer atits end sections and is free in its central section.
 4. The nanotubearray as claimed in one of claims 1 to 3, in which the subregions of thecatalyst layer are decoupled from one another and/or in which thenanotubes are decoupled from one another.
 5. The nanotube array asclaimed in one of claims 1 to 3, further comprising a circuit device, bymeans of which the nanotubes can be driven and/or read individually. 6.The nanotube array as claimed in one of claims 1 to 3, furthercomprising, at least one of the subregions of the catalyst layer is atleast partially surrounded by a further electrically insulating layer.7. The nanotube array as claimed in claim 6, in which the electricallyinsulating layer and the further electrically insulating layer, betweenwhich the catalyst layer is arranged, project laterally beyond thecatalyst layer, to form the pore which can be used to predetermine thedirection of growth of the nanotube parallel to the surface of thesubstrate.
 8. The nanotube array as claimed in claim 7, in which theelectrically insulating layer and/or the further electrically insulatinglayer is made from one or a combination of the materials silicon nitrideand silicon dioxide.
 9. The nanotube array as claimed in one of claims 1to 3, in which, furthermore, at least one of the subregions of thecatalyst layer is at least partially surrounded by a layer forpreventing diffusion.
 10. The nanotube array as claimed in claim 9, inwhich the layer for preventing diffusion is made from tantalum nitride.11. The nanotube array as claimed in one of claims 1 to 3, in which thecatalyst layer is made from the group consisting of nickel, iron andcobalt.
 12. The nanotube array as claimed in one of claims 1 to 3, inwhich the subregions of the catalyst layer are arranged parallel to oneanother.
 13. The nanotube array as claimed in one of claims 1 to 3, inwhich the array is used as a gas sensor.
 14. The nanotube array asclaimed in one of claims 1 to 3, also having a means, which isintegrated in the substrate, for recording the electrical resistance ofthe at least one nanotube.
 15. The nanotube array as claimed in one ofclaims 1 to 3, in which the nanotubes are carbon nanotubes.
 16. A methodfor producing a nanotube array, comprising: applying a catalyst layer tothe surface of the layer arrangement, the catalyst layer having one ormore subregions; and growing at least one nanotube on an uncovered partof the surface of a subregion of the catalyst layer, in such a mannerthat the at least one nanotube is arranged parallel to the surface ofthe layer arrangement, the direction of growth of the nanotube startingfrom the catalyst layer and parallel to the surface of the substratebeing predetermined by means of a pore.
 17. The method as claimed inclaim 16, further comprising: forming the layer arrangement by applyingan electrically insulating layer to a substrate.
 18. The method asclaimed in claim 16, further comprising: applying a further electricallyinsulating layer to at least part of the surface of the layerarrangement, in such a manner that the further electrically insulatinglayer at least partially covers at least one of the subregions of thecatalyst layer.
 19. The method as claimed in claims 16 to 18, furthercomprising: etching a trench into a surface region of the layerarrangement.
 20. The method as claimed in claims 16 to 19, furthercomprising: partially etching back the catalyst layer in such a mannerthat the electrically insulating layer and the further electricallyinsulating layer project laterally beyond the catalyst layer, with theresult that the pore which predetermines the direction of growth of thenanotube parallel to the surface of the substrate is produced.
 21. Amethod for producing a nanotube array, comprising, in this order:forming a layer arrangement by applying an electrically insulating layerto a substrate; applying a catalyst layer is applied to the surface ofthe layer arrangement, the catalyst layer having one or more subregions;applying a further electrically insulating layer to at least part of thesurface of the layer arrangement, in such a manner that the furtherelectrically insulating layer at least partially covers at least one ofthe subregions of the catalyst layer; etching a trench into a surfaceregion of the layer arrangement; partially etching back the catalystlayer in such a manner that the electrically insulating layer and thefurther electrically insulating layer project laterally beyond thecatalyst layer, with the result that the pore which predetermines thedirection of growth of the nanotube parallel to the surface of thesubstrate is produced; and growing at least one nanotube on an uncoveredpart of the surface of a subregion of the catalyst layer in such amanner that the at least one nanotube is arranged parallel to thesurface of the layer arrangement.
 22. A method for producing a nanotubearray, comprising, in this order: forming a layer arrangement byapplying an electrically insulating layer to a substrate; etching atrench into a surface region of the layer arrangement; applying acatalyst layer to the surface of the layer arrangement, the catalystlayer having one or more subregions; applying a further electricallyinsulating layer to at least part of the surface of the layerarrangement, in such a manner that the further electrically insulatinglayer at least partially covers at least one of the subregions of thecatalyst layer; etching a trench into a surface region of the layerarrangement; partially etching back the catalyst layer in such a mannerthat the electrically insulating layer and the further electricallyinsulating layer poroject laterally beyond the catalyst layer, with theresult that the port which predetermines the direction of growth of thenanotube parallel to the surface of the substrate is produced; andgrowing at least one nanotube on an uncovered part of the surface of asubregion of the catalyst layer in such a manner that the at least onenanotube is arranged parallel to the surface of the layer arrangement.23. The method as claimed in claim 16, further comprising at least onelayer for preventing diffusion is introduced at least in part between atleast one subregion of the catalyst layer and the layers which adjointhe at least one subregion of the catalyst layer.
 24. The method asclaimed in claim 18, further comprising the electrically insulatinglayer and/or the further electrically insulating layer is made from thegroup consisting of materials silicon nitride and silicon dioxide. 25.The method as claimed in claim 23 or 24, in which the layer forpreventing diffusion is made from tantalum nitride.
 26. The method asclaimed in claim 16, in which the catalyst layer is made from the groupconsisting of nickel, iron and cobalt.
 27. The method as claimed inclaim 16, in which the catalyst layer which has one or more subregionsis applied to the surface of the layer arrangement by first of all alayer of catalyst material being applied and this layer of catalystmaterial then being patterned by means of electron beam lithography. 28.The method as claimed in claim 16, in which the at least one nanotube isgrown on an uncovered part of the surface of a subregion of the catalystlayer by means of vapor phase epitaxy.
 29. The method as claimed inclaim 16, in which the at least one nanotube is a carbon nanotube.